NVLink Fusion: A Custom XPU, an NVIDIA Rack, and Where MediaTek Fits In (#AI)

When I wrote about the evolution of Google TPU, the logic was clear: a large cloud provider builds its own accelerator to fit the hardware more closely to its models and reduce its dependence on general-purpose GPUs.

NVIDIA's answer to this trend is rather elegant: fine, build your own XPU—and we will help assemble the rack around it on our architecture.

On August 31, 2026, NVIDIA and MediaTek announced an expansion of their partnership. NVIDIA purchased $3.5 billion in MediaTek convertible notes—debt securities that can be exchanged for shares under specified conditions. The technically more interesting part of the announcement is that MediaTek will help customers design and integrate custom AI accelerators, while NVLink Fusion will give those chips a path into NVIDIA rack-scale infrastructure.

Here, XPU is not one specific processor type. It is a generic name for a custom accelerator designed around a particular workload profile: training or inference, meaning the execution of an already trained model. A customer can bring its own microarchitecture or ask MediaTek to design it.

One NVIDIA connection option looks like this: custom XPU → UCIe → NVIDIA chiplet bridge → NVLink → NVSwitch → AI rack UCIe is an open interface between chiplets inside a multi-die system. It connects the XPU to NVIDIA's bridge, which brings the accelerator onto NVLink. NVSwitch joins many accelerators into one high-speed network. NVIDIA also offers building blocks for CPU/GPU connectivity, memory, and a common rack form factor—NVLink-C2C, NVHBM, and MGX. This architecture allows the system to share networking, power, cooling, and management; NVIDIA and MediaTek also say they will help test and debug the completed system before volume production.

In simpler terms, the customer designs the engine, while NVIDIA provides the roads and interchanges that allow an entire fleet of those machines to move.

This is how I would read NVLink Fusion: NVIDIA is not resisting the rise of custom chips at Google, AWS, and other large companies. It is trying to become the foundation layer for heterogeneous AI computing. The compute die may not come from NVIDIA, but data exchange between accelerators—and, with MGX, a significant part of the rack—can remain inside its ecosystem.

NVLink Fusion should not be confused with a fully open standard. The local UCIe boundary is open, while NVLink, the chiplet bridge, and NVSwitch remain proprietary NVIDIA technologies. Dependence therefore appears at the scale-up network layer and can extend into the rack architecture.

This is not only a MediaTek story. When NVIDIA launched NVLink Fusion on May 18, 2025, it also named Marvell, Alchip, Astera Labs, Synopsys, and Cadence as partners. AWS later said that Trainium4 is being designed with NVLink Fusion support.

NVIDIA says the architecture should shorten the path from a chip design to a working rack. That cannot yet be verified: the joint NVIDIA–MediaTek project has no named customer, launch date, or independent performance or total-cost-of-ownership data. The real test is still ahead: whether a production system appears in which the XPU is genuinely custom and NVLink Fusion genuinely speeds the path to operation. If it does, NVIDIA's moat will no longer run only around the GPU. It will run around the rack. And that seems more interesting than another FLOPS comparison.

#AI #Engineering #Architecture #Infrastructure #Hardware #Bigtech